2011.11.21 二位元加法器

                                                                      二位元加法器  

module top;
reg [1:0] A, B;
reg Cin;
wire[1:0] Sum;
adder2 M2(Cout, Sum, A, B, Cin);
initial
begin
A=2'd1;
B=2'd1;
Cin=1'd1;
end
endmodule
module adder2(Cout, Sum, A, B, Cin);
output Cout;
output [1:0] Sum;
input [1:0] A, B;
input Cin;
adder1 I1 (C0, Sum[0], A[0], B[0], Cin);
adder1 I2 (Cout, Sum[1], A[1], B[1], C0);
endmodule
module adder1(Cout, Sum, A, B, Cin);
output Cout,Sum;
input A,B,Cin;
and I1 (AandB, A, B);
xor I2 (AxorB, A, B);
and I3 (And1, AxorB, Cin);
or I4 (Cout, AandB, And1);
xor I5 (Sum, AxorB, Cin);
endmodule
module system_clock(clk);
paraclk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
meter PERIOD=100;
output clk;
reg endmodule



11/7 上課試做 一元加法器

module top;
system_clock #400 clock1(Cin);
system_clock #200 clock2(A);
system_clock #100 clock3(B);
adder 01(Cout,Sum,Cin,A,B);
endmodule
module adder(Cout,Sum,Cin,A,B);
input A,B,Cin;
output Cout,sum;
and I1(sel_01,A,B);
xor I2(sel_02,A,B);
and I3(sel_03,sel_02,Cin);
or I4(Cout,sel_01,sel_03);
xor I5(Sum,sel_02,Cin);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

2011.11.07 18:29