2011/12/19 期末上機考實做

1.     老師出題

2.     把0、1 填入 布林函數化簡

找出

E1=A1B1CD1      

E2=A1BC1    

E3=ABC

E4=ACD   

E5=AB1CD1

3.繪出邏輯電路

4.程式碼

module top;

system_clock #400 clock1(a);

system_clock #200 clock1(b);

system_clock #100 clock1(c);

system_clock #50 clock1(d);

number n1(e,a,b,c,d);

endmodule

module number(e,a,b,c,d);

input a,b,c,d;

output e;

wire a1,b1,c1,d1,w1,w2,w3,w4,w5;

not(a1,a);

not(b1,b);

not(c1,c);

not(d1,d);

and(w1,a1,b1,c,d1);

and(w2,a1,b,c1);

and(w3,a,b,c);

and(w4,a,c,d);

and(w5,a,b1,c1,d1);

or(e,w1,w2,w3,w4,w5);

endmodule

module system_clock(clk);

parameter PERIOD=100;

output clk;

reg clk;

initial

clk=0;

always

begin

#(PERIOD/2)clk=~clk;

end

always@(posedge clk)

if($time>1000)

$stop;

Endmodule

5.將程式碼 貼在筆記本 副檔名改為 .v 存檔

6. 用SynaptiCAD打開此程式 把檔案匯入

7.成果                                                              ↓↓↓

2011.11.21 二位元加法器

                                                                      二位元加法器  

module top;
reg [1:0] A, B;
reg Cin;
wire[1:0] Sum;
adder2 M2(Cout, Sum, A, B, Cin);
initial
begin
A=2'd1;
B=2'd1;
Cin=1'd1;
end
endmodule
module adder2(Cout, Sum, A, B, Cin);
output Cout;
output [1:0] Sum;
input [1:0] A, B;
input Cin;
adder1 I1 (C0, Sum[0], A[0], B[0], Cin);
adder1 I2 (Cout, Sum[1], A[1], B[1], C0);
endmodule
module adder1(Cout, Sum, A, B, Cin);
output Cout,Sum;
input A,B,Cin;
and I1 (AandB, A, B);
xor I2 (AxorB, A, B);
and I3 (And1, AxorB, Cin);
or I4 (Cout, AandB, And1);
xor I5 (Sum, AxorB, Cin);
endmodule
module system_clock(clk);
paraclk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
meter PERIOD=100;
output clk;
reg endmodule



11/7 上課試做 一元加法器

module top;
system_clock #400 clock1(Cin);
system_clock #200 clock2(A);
system_clock #100 clock3(B);
adder 01(Cout,Sum,Cin,A,B);
endmodule
module adder(Cout,Sum,Cin,A,B);
input A,B,Cin;
output Cout,sum;
and I1(sel_01,A,B);
xor I2(sel_02,A,B);
and I3(sel_03,sel_02,Cin);
or I4(Cout,sel_01,sel_03);
xor I5(Sum,sel_02,Cin);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

2011.11.07 18:29

10/17 課堂實作

module hello1;
initial $display("Hello Verilog");
endmodule
                                              ↓↓

2011.10.17 第一個作業

程式碼編號：

module top;

system_clock #400 clock1(A);

system_clock #200 clock2(B);
system_clock #100 clock3(SEL);

mux mml(OUT,A,B,SEL);

endmodule

module mux(OUT, A, B, SEL);

output OUT;
input A,B,SEL;
not I5 (sel_n, SEL);
and I6 (sel_a, A, SEL);
and I7 (sel_b, sel_n, B);
or I4 (OUT, sel_a, sel_b);
endmodule

module system_clock(clk);

parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule
                                                                         ↓時範圖