11/7 上課試做 一元加法器

module top;
system_clock #400 clock1(Cin);
system_clock #200 clock2(A);
system_clock #100 clock3(B);
adder 01(Cout,Sum,Cin,A,B);
endmodule
module adder(Cout,Sum,Cin,A,B);
input A,B,Cin;
output Cout,sum;
and I1(sel_01,A,B);
xor I2(sel_02,A,B);
and I3(sel_03,sel_02,Cin);
or I4(Cout,sel_01,sel_03);
xor I5(Sum,sel_02,Cin);
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
end
always@(posedge clk)
if($time>1000)
$stop;
endmodule

2011.11.07 18:29